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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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August 27, 1998  
GENERAL RELEASE SPECIFICATION  
The frequency, f  
of the EPO or external clock source is divided by two to pro-  
OSC  
duce the internal operating frequency, f . or f  
.
OP  
BUS  
Crystal Oscillator  
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel  
resonant crystal. The crystal manufacturer’s recommendations should be fol-  
lowed, as the crystal parameters determine the external component values  
required to provide maximum stability and reliable start-up. The load capacitance  
values used in the oscillator circuit design should include all stray capacitances.  
The crystal and components should be mounted as close as possible to the pins  
for start-up stabilization and to minimize output distortion.  
MCU  
MCU  
OSC1  
OSC2  
OSC1  
OSC2  
2MΩ  
Unconnected  
External Clock  
(b) External Clock Source Connection  
(a) Crystal or Ceramic Resonator Connections  
Figure 1-3. EPO Oscillator Connections  
Ceramic Resonator Oscillator  
In cost-sensitive applications, a ceramic resonator can be used in place of the  
crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The res-  
onator manufacturer’s recommendations should be followed, as the resonator  
parameters determine the external component values required for maximum sta-  
bility and reliable starting. The load capacitance values used in the oscillator cir-  
cuit design should include all stray capacitances. The ceramic resonator and  
components should be mounted as close as possible to the pins for start-up stabi-  
lization and to minimize output distortion.  
External Clock  
An external clock from another CMOS-compatible device can be connected to the  
OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b). This  
configuration is possible regardless of whether the crystal/ceramic resonator or  
internal VCO is enabled.  
1.6.3 IRQ/V  
PP  
The IRQ/V input pin drives the asynchronous IRQ interrupt function of the CPU.  
PP  
The IRQ interrupt function has a bit to provide either only negative edge-sensitive  
triggering or both negative edge-sensitive and low level-sensitive triggering. If the  
MC68HC05SB7  
REV 2.1  
GENERAL DESCRIPTION  
MOTOROLA  
1-5  
 
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