August 27, 1998
GENERAL RELEASE SPECIFICATION
RESET
ILLEGAL ADDR
V
V
RESET
DD
SS
WATCHDOG
SYSTEM
CORE TIMER
LOW VOLTAGE
RESET
OSCILLATOR AND
DIVIDE BY 2
V
DD
CPU CONTROL
68HC05 CPU
ALU
ESVEN
OSC1*
(PB2/CS0)
ACCUM
INDEX REG
ESV
CPU REGIS-
OSC2*
(PB3/CS1)
STK PTR
0 0 0 0 0 0 0 0 1 1
PC7
PC6
PC5
PC4
IRQ/V
PP
PROGRAM COUNTER
PA7/SDA1
PA6/SCL1
PA5/SDA0
PA4/SCL0
PA3/PWM3
PA2/PWM2
PA1/PWM1
PA0/PWM0
COND CODE REG 1 1 1 H I N Z C
4
4
SM-BUS SERIAL INTERFACE
10-BIT PWM
16-BIT TIMER
SCL
TCAP
TCSEL
PB7/AN0
PB6/AN1
PB5/AN2
PB4/AN3
PB3/CS1*
PB2/CS0*
PB1/TCAP
MUX
STATIC RAM - 224 BYTES
USER ROM - 6656 BYTES
PERSONALITY EPROM - 64 BITS
AN3:0
TCAP
TCMP
ICF
* Selected by Mask Option
CS1:0
4
TCAP
OCF
TOF
CURRENT SENSE
AMPLIFIER
2
CSA
COMPARATOR CONTROL
AND
INTERNAL TEMPERATURE
MULTIPLEXER
SENSOR AND BANDGAP REFERENCE
TM
VM
V
DD
CAP
Figure 1-1. MC68HC05SB7 Block Diagram
MC68HC05SB7
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-3
FREESCALE [ Freescale ]
