GENERAL RELEASE SPECIFICATION
August 27, 1998
CPF
This read-only flag bit is set when the voltage on the positive input of compara-
tor rises above the voltage on its negative input. This bit is reset by writing a
logical one to the CPFR reset bit in the ASR.This bit is cleared by a reset of the
device.
1 = The voltage on positive input of comparator was above the voltage
on its negative input since CPF had been cleared.
0 = The voltage on positive input of comparator has not been above the
voltage on its negative input since CPF had been cleared.
CPFR
Writing a logical one to this write-only flag clears the CPF flag in the ASR. Writ-
ing a logical zero to this bit has no effect. Reading the CPFR bit will return a
logical zero. By default this bit looks cleared following a reset of the device.
1 = Clears the CPF flag bit.
0 = No effect.
NOTE
The CPFR bit should be written with a logical one following a power up of the
comparator. This will clear out any latched CPF flag bit which might have been set
during the slower power up sequence of the analog circuitry.
If both inputs to the comparator are above the maximum common-mode input
voltage (V –1.5V) the output of the comparator is indeterminate and may set the
DD
comparator flag. Applying a reset to the device may only temporarily clear this flag
as long as both inputs of a comparator remain above the maximum common-
mode input voltages.
MOTOROLA
15-18
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
