GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-2. Channel Select Bus Combinations
Analog Multiplex Registers
(AMUX1 and AMUX2)
Channel Select Bus Connected to:
I
V
R
E
F
M M M M M M M M
U U U U U U U U
X X X X X X X X
7 6 5 4 3 2 1 0
B
R
E
F
V
V
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
V
SS
DD
IB
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
ON
ON
ON
ON
ON
ON
ON
ON
ON
Z
ON
ON
ON
ON
ON
ON
ON
ON
ON
Z
ON
ON
ON
ON
ON
ON
ON
ON
ON
Z
ON
ON
ON
ON
ON
ON
ON
ON
ON
Z
Z
ON
Z
ON
Z
ON
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
ON
ON
ON
ON
ON
ON
ON
ON
Z
Z
Z
ON
Z
Z
Z
ON
ON
Z
Z
Z
ON
Z
Z
ON
ON
ON
ON
Z
Z
Z
ON
Z
Z
ON
ON
Z
Z
ON
Z
ON
Z
1
0
ON
Z
Z
Z
Z
Z
Z
Z
Z
X = Don’t Care
= High Impedance
Z
15.2 ANALOG CONTROL REGISTER
The Analog Control Register (ACR) controls the power up, interrupt and flag oper-
ation. The analog subsystem draws about 470 µA of current while it is operating.
The resulting power consumption can be reduced by powering down the analog
subsystem when not in use. This can be done by clearing two enable bits (ISEN
and CPEN) in the ACR at $001D. Since these bits are cleared following a reset,
the voltage comparator and the charge current source will be powered down fol-
lowing a reset of the device.
The control bits in the ACR are shown in Figure 15-2. All the bits in this register
are cleared by a reset of the device.
BIT 7
CHG
0
BIT 6
ATD2
0
BIT 5
ATD1
0
BIT 4
ICEN
0
BIT 3
CPIE
0
BIT 2
CPEN
0
BIT 1
0
BIT 0
ISEN
0
ACR
R
$001D
W
reset:
Figure 15-5. Analog Control Register (ACR)
MOTOROLA
15-14
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
