GENERAL RELEASE SPECIFICATION
August 27, 1998
Table 15-5. Sample Conversion Timing
V
f
t
CHG
(µs)
C
(µF)
MAX
OSC
Bits Counts
A/D Method
Clock Source
(VDC)
(MHz)
Software Loop (10 cycles)
Mode 0 (manual)
8
256
3.5
Ext Pin Oscillator
VCO
2.0
2560
0.073
0.5
1.0
2.0
4.0
0.5
1.0
2.0
4.0
0.5
1.0
2.0
4.0
4096
2048
1024
512
0.117
0.059
0.029
0.015
0.468
0.234
0.117
0.059
1.872
0.936
0.468
0.234
Programmable Timer,
Mode 1 (TOF to ICF)
8
256
3.5
3.5
3.5
Ext Pin Oscillator
VCO
16384
8192
4096
2048
65536
32768
16384
8192
Programmable Timer,
Mode 1 (TOF to ICF)
10
12
1024
4096
Ext Pin Oscillator
VCO
Programmable Timer,
Mode 1 (TOF to ICF)
Ext Pin Oscillator
The general architecture of the MC68HC05SB7 and mode selection bits in the
ACR allow four methods based on simple single-slope A/D conversion. Each of
these methods is shown in the following figures:
•
•
•
•
Manual start and stop (Mode 0) Figure 15-8.
Manual start and automatic discharge (Mode 1) Figure 15-9.
Automatic start and stop from TOF to ICF (Mode 2) Figure 15-10.
Automatic start and stop from OCF to ICF (Mode 3) Figure 15-11.
The description of the signals and parameters used in these figures are given in
Table 15-4.
MOTOROLA
15-22
ANALOG SUBSYSTEM
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
