August 27, 1998
GENERAL RELEASE SPECIFICATION
CPEN
The CPEN enable bit will power down voltage comparator in the analog sub-
system. Powering down a comparator will drop the supply current by about
100µA. This bit is cleared by a reset of the device.
1 = Writing a logical one powers up voltage comparator.
0 = Writing a logical zero powers down voltage comparator
NOTE
The voltage comparator powers up slower than digital logic; and its output may go
through indeterminate states which might set the CPF flag. It is therefore
recommended to power up the charge current source first (ISEN); then to power
up the comparator, and finally clear the bit by writing a logic one to the CPFR bit in
the ACR.
ISEN
The ISEN enable bit will power down the charge current source and disable the
discharge device in the analog subsystem. Powering down the current source
will drop the supply current by about 200 µA.This bit is cleared by a reset of the
device.
1 = Writing a logical one powers up the ramping current source and
enables the discharge device on the CAP pin.
0 = Writing a logical zero powers down the ramping current source and
disables the discharge device on the CAP pin.
NOTE
The analog subsystem has support circuitry which draws about 70µA of current.
This current will be powered down if the comparator and the charge current
source are powered down (ISEN and CPEN all cleared). Powering up the
comparator or the charge current source will activate the support circuitry.
15.3 ANALOG STATUS REGISTER
The Analog Status Register (ASR) controls the interrupt and flag operation. The
control bits in the ASR are shown in Figure 15-2. All the bits in this register are
cleared by a reset of the device.
BIT 7
CPF
BIT 6
BIT 5
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
ASR
R
0
CPFR
0
$001E
W
reset:
0
0
0
0
0
0
0
Figure 15-6. Analog Status Register
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-17
FREESCALE [ Freescale ]
