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68HC705SB7 参数 Datasheet PDF下载

68HC705SB7图片预览
型号: 68HC705SB7
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 170 页 / 1982 K
品牌: FREESCALE [ Freescale ]
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August 27, 1998  
GENERAL RELEASE SPECIFICATION  
NOTE  
Sufficient time should be allowed to discharge the external capacitor or  
subsequent charge times will be shortened with resultant errors in timing  
conversion.  
NOTE  
If the unknown voltage applied to the comparator is greater than its common-  
mode range (V –1.5 volts) the external capacitor will try to charge to the same  
DD  
level. This will cause both comparator inputs to be above the common-mode  
range and the output will be indeterminate. All A/D conversion software methods  
should have a maximum time check to determine if this case is occurring.  
Table 15-4. A/D Conversion Signals and Definitions  
Name  
Function  
Conditions  
I
Charging current on external ramping capacitor  
Discharge current on external ramping capacitor  
Voltage on external ramping capacitor  
I
= 80 - 120 µA  
CHG  
CHG  
I
I
> 1 mA  
DIS  
DIS  
V
V
< V  
< (V – 1.5)  
CAP  
SS  
CAP DD  
V
Voltage of unknown on (–) input of voltage comparator  
Maximum voltage on external ramping capacitor  
TIme to charge external capacitor  
V
< V < (V –1.5)  
X
SS X DD  
V
V
= V – 1.0  
MAX  
CHG  
MAX DD  
t
t from V to V  
SS X  
t
Time to discharge external capacitor  
t from V  
to V  
DIS  
MAX SS  
C
Capacitance of external ramping capacitor  
0.001 to 1.000 µF  
N
Number of counts for I  
to charge C to V  
0 to 65536  
CHG  
X
f
÷ loop time for software timing  
OSC  
P
Prescaler into timing function  
Clock source frequency (excluding any prescaling)  
f
÷ 8 for Core Timer  
OSC  
f
÷ 8 for Programmable TImer  
OSC  
f
0 to 4.2 MHz  
OSC  
Table 15-5 gives examples of voltage ranges, resolution, ramp times and capaci-  
tor sizes for various conversion methods.  
MC68HC05SB7  
REV 2.1  
ANALOG SUBSYSTEM  
MOTOROLA  
15-21  
 
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