August 27, 1998
GENERAL RELEASE SPECIFICATION
15.1 ANALOG MULTIPLEX REGISTERS
The Analog Multiplex Registers (AMUX1 and AMUX2) control the general inter-
connection and operation. The control bits in AMUX1 and AMUX2 are shown in
Figure 15-2 and Figure 15-2 respectively.
BIT 7
HOLD
1
BIT 6
DHOLD
0
BIT 5
INV
0
BIT 4
VREF
0
BIT 3
MUX3
0
BIT 2
MUX2
0
BIT 1
MUX1
0
BIT 0
MUX0
0
AMUX1
$0003
R
W
reset:
Figure 15-2. Analog Multiplex Register 1 (AMUX1)
BIT 7
0
BIT 6
BIT 5
0
BIT 4
IBREF
0
BIT 3
MUX7
0
BIT 2
MUX6
0
BIT 1
MUX5
0
BIT 0
MUX4
0
AMUX2
$0007
R
W
reset:
0
0
0
Figure 15-3. Analog Multiplex Register 2 (AMUX2)
HOLD, DHOLD
These read/write bits control the source connection to the input to the negative
input of voltage comparator shown in Figure 15-1. This allows the channel
selection bus or the 1:2 divided channel selection bus to charge the internal
sample capacitor and to also be presented to comparator. The decoding of
these sources is given in Table 15-1. During a reset the HOLD bit is set and the
DHOLD bit is cleared, which connects the internal sample capacitor to the
channel selection bus. And since a reset also clears the MUX0:7 bits then the
channel selection bus will be connected to V and the internal sample capaci-
SS
tor will be discharged to V following the reset.
SS
Table 15-1. Comparator Input Sources
HOLD
DHOLD
Case
Source To Negative Input of Comparator
Internal sample capacitor connected to only the neg-
ative input of comparator; and subjected to a very
low leakage current.
0
0
Sample Hold
Signal to channel selection bus is divided by 2 and
connected to both the internal sample capacitor and
negative input of comparator.
0
1
Divided Input
Signal to channel selection bus is connected directly
to both the internal sample capacitor and negative
input of comparator.
Direct
Input
1
1
0
1
Not allowed
—
MC68HC05SB7
REV 2.1
ANALOG SUBSYSTEM
MOTOROLA
15-3
FREESCALE [ Freescale ]
