Freescale Semiconductor, Inc.
Op e ra ting Mod e s
• An external interrupt signal on a port A external interrupt pin — If
selected by the PIRQ bit in the MOR, a low-to-high transition on a
PA3–PA0 pin loads the program counter with the contents of
locations $1FFA and $1FFB.
• External reset — A logic zero on the RESET pin resets the MCU
and loads the program counter with the contents of locations
$1FFE and $1FFF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 16 or 4064 internal bus cycles, depending on the
state of the DELAY bit in the MOR.
NOTE: Execution of the STOP instruction without setting the SWAIT bit in the
MOR will cause the oscillators to stop, and, therefore, disable the COP
watchdog timer. If the COP watchdog timer is to be used, stop mode
should be changed to halt mode as described in 6.4.3 Halt Mode.
6.4.2 Wa it Mod e
The WAIT instruction puts the MCU in a low-power wait mode which
consumes more power than the stop mode and affects the MCU as
follows:
• Enables interrupts by clearing the I bit in the condition code
register
• Enables external interrupts by setting the IRQE bit in the IRQ
status and control register
• Stops the CPU clock which drives the address and data buses, but
allows the selected oscillator to continue to clock the core timer,
programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O
lines.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Operating Modes
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