Freescale Semiconductor, Inc.
Op e ra ting Mod e s
6.4.3 Ha lt Mod e
The STOP instruction puts the MCU in halt mode if selected by the
SWAIT bit in the MOR. Halt mode is identical to wait mode, except that
a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can
be selected by the DELAY bit in the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP
watchdog cannot be turned off inadvertently by a STOP instruction.
6.4.4 Da ta -Re te ntion Mod e
In the data-retention mode, the MCU retains RAM contents and CPU
register contents at V voltages as low as 2.0 Vdc. The data retention
DD
feature allows the MCU to remain in a low-power consumption state
during which it retains data, but the CPU cannot execute instructions.
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic zero.
2. Lower the V voltage. The RESET pin must remain low
DD
continuously during data retention mode.
To take the MCU out of the data retention mode:
1. Return V to normal operating voltage.
DD
2. Return the RESET pin to a logic one.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Operating Modes
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