Freescale Semiconductor, Inc.
Inte rrup ts
components like filter capacitors and a crystal or ceramic resonator
and consumes more power. The selection and enable conditions for
these two oscillators are shown in Table 4-2.
Table 4-2. Oscillator Selection
Internal
Low-Power
Oscillator
(LPO)
External
Pin
Oscillator
(EPO)
Oscillator
Selected
by CPU
Power
Consumption
OM2 OM1
0
0
1
1
0
1
0
1
Internal
External
Internal
Internal
Enabled
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Lowest
Normal
Lowest
Normal
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started and allowed to stabilize while the LPO still clocks the MCU.
The reset state is for OM1 to be cleared and OM2 to be set, which
selects the LPO and disables the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Writing to the IRQF bit has no effect.
Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
The following conditions set the IRQ flag:
• An external interrupt signal on the IRQ/V pin
PP
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
when the PA0–PA3 pins are enabled by the PIRQ bit in the
MOR to serve as external interrupt sources.
The following conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic one is written to the IRQR bit
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Interrupts
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
