Freescale Semiconductor, Inc.
Interrupts
External Interrupts
With the edge- and level-sensitive trigger MOR option, a falling edge or
a low level on the IRQ/V pin latches an external interrupt request. The
PP
edge- and level-sensitive trigger MOR option allows connection to the
IRQ/V pin of multiple wired-OR interrupt sources. As long as any
PP
source is holding the IRQ low, an external interrupt request is present,
and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the
IRQ/V pin latches an external interrupt request. A subsequent
PP
interrupt request can be latched only after the voltage level on the
IRQ/V pin returns to a logic one and then falls again to logic zero.
PP
V
PP TO
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/V
PP
PA3
PA2
PA1
PA0
V
DD
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER ($000D)
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
Figure 4-3. External Interrupt Logic
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Interrupts
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