Freescale Semiconductor, Inc.
Inte rrup ts
4.5 Softwa re Inte rrup t
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.6 Exte rna l Inte rrup ts
These sources can generate external interrupts:
• IRQ/V pin
PP
• PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables these external
interrupts.
4.6.1 IRQ/ V Pin
PP
An interrupt signal on the IRQ/V pin latches an external interrupt
PP
request. To help clean up slow edges, the input from the IRQ/V pin is
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processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register (ISCR). If the I bit is clear and the IRQE
bit is set, then the CPU begins the interrupt sequence. The CPU clears
the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt,
the CPU can recognize the new interrupt request. Figure 4-3 shows the
logic for external interrupts.
NOTE: If the IRQ/V pin is not in use, it should be connected to the V pin.
PP
DD
The IRQ/V pin can be negative edge-triggered only or negative edge-
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and low level-triggered. External interrupt sensitivity is programmed with
the LEVEL bit in the mask option register (MOR).
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Interrupts
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