Freescale Semiconductor, Inc.
Interrupts
Interrupt Vectors
Table 4-1. Reset/Interrupt Vector Addresses
MOR
Control
Bit
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
Function
Source
Power-On Logic
RESET Pin
Low-Voltage Reset
Illegal Address Reset
—
Reset
—
—
—
—
1
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
1
COP Watchdog
COPEN
Software
Interrupt
(SWI)
Same Priority
As Instruction
User Code
—
—
IRQ/V Pin
PP
PA3 Pin
PA2 Pin
PA1 Pin
PA0 Pin
External
Interrupt (IRQ)
I Bit
IRQE Bit
2
2
PIRQ
Core Timer
Interrupts
TOF Bit
RTIF Bit
TOFE Bit
RTIE Bit
—
—
I Bit
I Bit
3
4
$1FF8–$1FF9
$1FF6–$1FF7
Programmable
Timer
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
Interrupts
Serial
Interrupt
SPIF Bit
—
—
I Bit
I Bit
SPIE Bit
CPIE Bit
5
6
$1FF4–$1FF5
$1FF2–$1FF3
Analog
Interrupt
CPF1 Bit
CPF2 Bit
NOTES:
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
NOTE: If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
actually interrupt a lower priority interrupt service routine unless the
lower priority interrupt service routine clears the I bit.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Interrupts
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