Freescale Semiconductor, Inc.
Prog ra m m a b le Tim e r
A software example of this procedure is shown in Table 11-1.
Table 11-1. Output Compare Initialization Example
9B
...
SEI
...
DISABLE INTERRUPTS
.....
...
...
.....
B7
B6
BF
...
16
13
17
STA
LDA
STX
...
OCRH INHIBIT OUTPUT COMPARE
TSR
ARM OCF FLAG FOR CLEARING
OCRL READY FOR NEXT COMPARE, OCF CLEARED
.....
...
...
.....
9A
CLI
ENABLE INTERRUPTS
11.7 Tim e r Control Re g iste r (TCR)
The timer control register shown in Figure 11-10, performs the following
functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit
which is unaffected.
$0012
Read:
Write:
Reset:
Bit 7
ICIE
0
6
OCIE
0
5
TOIE
0
4
0
3
0
2
0
1
IEDG
U
Bit 0
OLVL
0
0
0
0
= Unimplemented
U = Unaffected
Figure 11-10. Timer Control Register (TCR)
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Programmable Timer
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