Freescale Semiconductor, Inc.
Prog ra m m a b le Tim e r
11.2 Introd uc tion
The MC68HC705JJ7/MC68HC705JP7 MCU contains a 16-bit
programmable timer with an input capture function and an output
compare function as shown by the block diagram in Figure 11-1.
The basis of the capture/compare timer is a 16-bit free-running counter
which increases in count with every four internal bus clock cycles. The
counter is the timing reference for the input capture and output compare
functions. The input capture and output compare functions provide a
means to latch the times at which external events occur, to measure
input waveforms, and to generate output waveforms and timing delays.
Software can read the value in the 16-bit free-running counter at any
time without affecting the counter sequence.
The I/O registers for the input capture and output compare functions are
pairs of 8-bit registers, because of the 16-bit timer architecture used.
Each register pair contains the high and low bytes of that function.
Generally, accessing the low byte of a specific timer function allows full
control of that function; however, an access of the high byte inhibits that
specific timer function until the low byte is also accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-
four prescaler, the counter rolls over every 262,144 internal clock cycles
(every 524,288 oscillator clock cycles). Timer resolution with a 4-MHz
crystal oscillator is 2 microsecond/count.
The interrupt capability, the input capture edge, and the output compare
state are controlled by the timer control register (TCR) located at $0012,
and the status of the interrupt flags can be read from the timer status
register (TSR) located at $0013.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Programmable Timer
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