Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 9. Sim p le Se ria l Inte rfa c e
9.1 Conte nts
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
9.3
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . .140
9.3.1
9.3.2
9.3.3
9.4
SIOP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
SIOP Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . .141
SIOP Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . .144
SIOP Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . .145
9.4.1
9.4.2
9.4.3
9.2 Introd uc tion
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications with peripheral devices or other
MCUs. SIOP is implemented as a 3-wire master/slave system with serial
clock (SCK), serial data input (SDI), and serial data output (SDO). A
block diagram of the SIOP is shown in Figure 9-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in the SCR), the port B data direction and
data registers are bypassed by the SIOP. The port B data direction and
data registers will remain accessible and can be altered by the
application software, but these actions will not affect the SIOP
transmitted or received data.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Simple Serial Interface
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