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68HC705JJ7_1 参数 Datasheet PDF下载

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型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Simple Serial Interface  
SIOP Registers  
9.4 SIOP Re g iste rs  
The SIOP is programmed and controlled by the SIOP control register  
(SCR) located at address $000A, the SIOP status register (SSR) located  
at address $000B, and the SIOP data register (SDR) located at address  
$000C.  
9.4.1 SIOP Control Re g iste r (SCR)  
The SIOP control register (SCR) is located at address $000A and  
contains seven control bits and a write-only reset of the interrupt flag.  
Figure 9-4 shows the position of each bit in the register and indicates  
the value of each bit after reset.  
$000A  
Read:  
Write:  
Reset:  
Bit 7  
SPIE  
0
6
SPE  
0
5
LSBF  
0
4
MSTR  
0
3
0
2
CPHA  
0
1
SPR1  
0
Bit 0  
SPR0  
0
SPIR  
0
Figure 9-4. SIOP Control Register (SCR)  
SPIE — Serial Peripheral Interrupt Enable  
The SPIE bit enables the SIOP to generate an interrupt whenever the  
SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the  
state of the SPIF flag bit and will not terminate a serial interrupt once  
the interrupt sequence has started. Reset clears the SPIE bit.  
1 = Serial interrupt enabled  
0 = Serial interrupt disabled  
NOTE: If the SPIE bit is cleared just after the serial interrupt sequence has  
started (for instance, the CPU status is being stacked), then the CPU will  
be unable to determine the source of the interrupt and will vector to the  
reset vector as a default.  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
General Release Specification  
Simple Serial Interface  
For More Information On This Product,  
Go to: www.freescale.com  
 
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