Freescale Semiconductor, Inc.
Analog Subsystem
Voltage Comparator Features
8.8 Volta g e Com p a ra tor Fe a ture s
The two internal comparators can be used as simple voltage
comparators if set up as described in Table 8-8. Both comparators can
be active in the Wait mode; and can directly restart the part by means of
the analog interrupt. Both comparators can also be active in the stop
mode, but cannot directly restart the part. However, the comparators can
directly drive PB4 which can then be connected externally to activate
either a port interrupt on the PA0:3 pins or the IRQ/V pin.
PP
Table 8-8. Voltage Comparator Setup Conditions
Prog. Timer
Input
Capture
Source
Current Discharge
Port B Pin
Pulldowns
Disabled
Port B Pin
as Inputs
Comparator Source
Device
Enable
Disable
Not
Affected
Not
Affected
DDRB2 = 0 PDIB2 = 1
DDRB3 = 0 PDIB3 = 1
Not
Affected
1
2
DDRB0 = 0 PDIB0 = 1
DDRB1 = 0 PDIB1 = 1
ICEN = 0
IEDG = 1
ISEN = 0 ISEN = 0
8.8.1 Volta g e Com p a ra tor 1
Voltage comparator 1 is always connected to two of the port B I/O pins.
These pins should be configured as inputs and have their software
programmable pulldowns disabled. Also, the negative input of voltage
comparator 1 is connected to the PB3/AN3/TCAP and shared with the
input capture function of the 16-bit programmable timer. Therefore, the
timer input capture interrupt should be disabled so that changes in the
voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture
interrupts.
The output of comparator 1 can be connected to the port logic driving the
PB4/AN4/TCMP/CMP1 pin such that the output of the comparator is
ORed with the PB4 data bit and the OLVL bit from the 16-bit timer. This
capability requires that the OPT bit is set in the COPR at location $1FF0
and the COE1 bit is set in the ASR at location $001E.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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