Freescale Semiconductor, Inc.
Analog Subsystem
Analog Status Register
COE1
This read-write bit controls the output of comparator 1 to the PB4 pin.
It is not active unless the OPT bit in the COPR at location $1FF0 is
set. Any reads of the COE1 bit location return a logical zero if the OPT
bit is clear. The COE1 bit is cleared by a reset of the device.
1 = Enables the output of comparator 1 to be ORed with the PB4
data bit and OLVL bit, if the DDRB4 bit is also set.
0 = Disables the output of comparator 1 from affecting the PB4 pin.
CMP2
This read-only bit shows the state of comparator 2 during the time that
the bit is read. This bit is therefore the current state of the comparator
without any latched history. The CMP2 bit will be high if the voltage
on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin,
regardless of the state of the INV bit in the AMUX register. Since a
reset disables comparator 2, this bit returns a logical zero following a
reset of the device.
1 = The voltage on the positive input on comparator 2 is higher than
the voltage on the negative input of comparator 2
0 = The voltage on the positive input on comparator 2 is lower than
the voltage on the negative input of comparator 2
CMP1
This read-only bit shows the state of comparator 1 during the time that
the bit is read. This bit is therefore the current state of the comparator
without any latched history. The CMP1 bit will be high if the voltage
on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP
pin, regardless of the state of the INV bit in the AMUX register. Since
a reset disables comparator 1, this bit returns a logical zero following
a reset of the device.
1 = The voltage on the positive input on comparator 1 is higher than
the voltage on the negative input of comparator 1
0 = The voltage on the positive input on comparator 1 is lower than
the voltage on the negative input of comparator 1
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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