Freescale Semiconductor, Inc.
Analog Subsystem
A/D Conversion Methods
Table 8-4 gives the range of values of each parameter in the A/D timing
conversion; and Table 8-5 gives some A/D conversion examples for
several bit resolutions.
Table 8-4. A/D Conversion Parameters
Name
Function
Min
Typ
—
Max
Units
V
Unknown voltage on channel selection bus
Charging voltage on external capacitor
Maximum charging voltage on external capacitor
Charging current on external ramping capacitor
V
V
V
V
–1.5
V
V
V
X
SS
SS
DD
DD
DD
V
V
—
–1.5
–1.5
CAP
MAX
V
—
—
Refer to 15.10 Analog Subsystem
I
V
V
= 3 VDC
= 5 VDC
Characteristics (5.0 Vdc) and 15.11 Analog
CHG
DD
DD
Subsystem Characteristics (3.0 Vdc)
Refer to 15.10 Analog Subsystem
Characteristics (5.0 Vdc) and 15.11 Analog
Subsystem Characteristics (3.0 Vdc)
I
Discharge current on external ramping capacitor
DIS
Time to charge external capacitor
(100 kHz < f
4-bit result
6-bit result
8-bit result
10-bit result
12-bit result
< 4.0 MHz)
OSC
0.032
0.128
0.512
2.048
8.192
0.128
0.512
2.048
8.196
32.768
2.56
10.24
40.96
t
ms
CHG
(1)
120
(1)
120
t
Time to discharge external capacitor, C
—
0.0001
1
5
10
2.0
ms/µF
µF
DIS
EXT
C
Capacitance of external ramping capacitor
Number of counts for I to charge C
0.1
EXT
N
to V
X
1024
65536
counts
CHG
EXT
Prescaler into timing function (÷ P)
Using core timer
Using 16-bit programmable timer
Using software loops
8
8
24
8
8
8
8
P
÷ P
user defined user defined
Clock source frequency
(excluding any prescaling)
Refer to 15.12 Control Timing (5.0 Vdc)
and 15.13 Control Timing (3.0 Vdc)
f
OSC
1. Limited by requirement for CEXT to be less than 2.0 µF.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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