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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Ana log Sub syste m  
8.6 A/ D Conve rsion Me thod s  
The control bits in the ACR provide various options to charge or  
discharge current through the PB0/AN0 pin in order to perform single-  
slope A/D conversions using an external capacitor from the PB0/AN0 pin  
to V as shown in Figure 8-7. The various A/D conversion triggering  
SS  
options are given in Table 8-3.  
C x V  
I
X
Charge Time =  
VDD –1.5 Vdc  
UNKNOWN VOLTAGE ON (–) INPUT  
VOLTAGE ON  
CAPACITOR  
CONNECTED  
TO (+) INPUT  
CHARGE TIME  
TO MATCH UNKNOWN  
DISCHARGE TIME  
TO RESET CAPACITOR  
MAXIMUM CHARGE TIME  
TO VDD –1.5 Vdc  
+ 5 V  
V
DD  
PB4/AN4  
PB3/AN3  
PB2/AN2  
PB1/AN1  
PB0/AN0  
UNKNOWN  
OR REFERENCE  
SIGNALS  
MC68HC705JJ7  
MC68HC705JP7  
V
SS  
RAMP  
CAP  
Figure 8-7. Single-Slope A/D Conversion Method  
The top three bits of the ACR control the charging and discharging  
current into or out of the PB0/AN0 pin. These three bits will have no  
effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing  
of the ISEN bit will immediately disable both the charge current source  
and the discharge device. Since all these bits and the ISEN bit are  
General Release Specification  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
Analog Subsystem  
For More Information On This Product,  
Go to: www.freescale.com  
 
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