Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
SECTION 9
COMPUTER OPERATING PROPERLY (COP)
This device includes a watchdog COP feature as a mask option. The COP is
implemented with an 18-bit ripple counter. This provides a timeout period of 64
milliseconds at a bus rate of 2 MHz. If the COP should timeout, a system reset
will occur and the device will be re-initialized in the same fashion as a power-on
reset (POR) or external reset.
9.1
Resetting The COP
Preventing a COP reset is done by writing a zero to the COPR bit. This action will
reset the counter and begin the timeout period again. The COPR bit is bit 0 of
address $1FF0. A read of address $1FF0 will access the user-defined ROM data
at that location.
9.2
9.3
COP During Wait or Halt Mode
The COP will continue to operate normally during wait or halt mode. The software
should pull the device out of wait or halt mode periodically and reset the COP by
writing a logic zero to the COPR bit to prevent a COP reset.
COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off for the
entire device. The COP counter will be reset when stop mode is entered. If a
reset is used to exit stop mode, the COP counter will be reset after the 4064
cycles of delay after stop mode. If an IRQ is used to exit stop mode, the COP
counter will not be reset after the 4064-cycle delay and will have that many cycles
already counted when control is returned to the program.
NOTE
The halt mode is not intended for normal use. This feature is
provided to keep the COP watchdog timer active in the event a
STOP instruction is inadvertently executed.
COMPUTER OPERATING PROPERLY (COP)
Rev. 2.0
9-1
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