Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
SECTION 11
INSTRUCTION SET
This section describes the M68HC05P4A addressing modes and instruction
types.
11.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The
addressing modes define the manner in which the CPU finds the data required to
execute an instruction. The eight addressing modes are the following:
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Inherent
Immediate
Direct
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Relative
11.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry flag (SEC) and increment accumulator (INCA).
Inherent instructions require no memory address and are one byte long.
INSTRUCTION SET
Rev. 2.0
11-1
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