Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
In master mode, the format is identical except that the SCK pin is an output and
the shift clock now originates internally. The master mode transmission frequency
is fixed at E/4.
7.1.2 Serial Data Out (SDO)
A mask programmable option will be included to allow data to be transmitted in
either MSB first format or LSB first format. In either case, the state of the SDO pin
always will reflect the value of the first bit received on the previous transmission if
there was one. Prior to enabling the SIOP, PB5 can be initialized to determine the
beginning state if necessary. While the SIOP is enabled, PB5 can not be used as
a standard output since that pin is coupled to the last stage of the serial shift
register. On the first falling edge of SCK, the first data bit to be shifted out is
presented to the output pin.
7.1.3 Serial Data In (SDI)
The SDI pin becomes an input as soon as the SIOP is enabled. New data may be
presented to the SDI pin on the falling edge of SCK. Valid data must be present at
least 100 ns before the rising edge of the clock and remain valid for 100 ns after
the edge.
SCK
BIT 1
BIT 1
BIT 2
BIT 2
BIT 3
BIT 3
BIT 7
BIT 7
BIT 8
BIT 8
SDO
SDI
7-2
Rev. 2.0
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