Freescale Semiconductor, Inc.
CPU Core
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-bit
state.
Table 3-1. Vector Address for Interrupts and Reset
Flag
Name
CPU
Interrupt
Register
Interrupts
Vector Address
N/A
N/A
N/A
N/A
Reset
RESET
SWI
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
Software
N/A
N/A
External Interrupt
Timer Overflow
RQ
TCSR
TOF
RTIF
CPIF
TIMER
IMER
CPI
Real Time Interrupt
Custom Periodic Interrupt
CPICSR
3.7.1 Ha rd wa re Controlle d Inte rrup t Se q ue nc e
The following three functions (RESET, STOP, and WAIT) are not in the
strictest sense an interrupt; however, they are acted upon in a similar
manner. See Figure 3-1 and Figure 3-2. A discussion is provided below.
1. RESET - A low input on the RESET input pin causes the program
to vector to its starting address which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset as previously described in
3.6 Resets.
2. STOP - The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT - The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ), or
Timer interrupt. There are no special wait vectors for these
individual interrupts.
General Release Specification
MC68HC05E1 — Revision 2.0
CPU Core
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