Freescale Semiconductor, Inc.
CPU Core
Interrupts
3.7.3 Exte rna l Inte rrup t
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced by the interrupt
service routine located at the address specified by the contents of
$1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger, or an
edge-sensitive-only trigger is available as a mask option.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
3.7.4 Tim e r Inte rrup t
There are two different timer interrupt flags that cause a timer interrupt
whenever they are set and enabled. The interrupt flags and enable bits
are located in the Timer Control and Status Register (TCSR). Either of
these interrupts will vector to the same interrupt service routine, located
at the address specified by the contents of memory location $1FF8 and
$1FF9. See 6.3.1 Timer Control and Status Register (TCSR) $08.
3.7.5 Custom Pe irod ic Inte rrup t (CPI)
The CPI flag and enable bits are located in the CPI Control and Status
Register (CPICSR). A CPI interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
location $1FF6 and $1FF7. See 6.5 Custom Periodic Interrupt.
MC68HC05E1 — Revision 2.0
General Release Specification
CPU Core
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