Freescale Semiconductor, Inc.
CPU Core
3.5.10 Inhe re nt
In the inherent addressing mode, all the information necessary to
execute the instruction is contained in the opcode. Operations specifying
only the index register and/or accumulator as well as the control
instructions with no other arguments are included in this mode. These
instructions are one byte long.
3.6 Re se ts
The MCU can be reset three ways: by the initial power-on reset function,
by an active low input to the RESET pin, by a COP watchdog-timer reset,
and by the ILADR bit being set in the test register.
3.6.1 Powe r-On Re se t (POR)
An internal reset is generated on power-up to allow the internal clock
generator to stabilize. The power-on reset is strictly for power turn-on
conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (t ) oscillator
cyc
stabilization delay after the oscillator becomes active. If the RESET pin
is low at the end of this 4064 cycle delay, the MCU will remain in the
reset condition until RESET goes high.
3.6.2 RESET Pin
The MCU is reset when a logic zero is applied to the RESET input for a
period of one and one-half machine cycles (t ). RESET is an input-only
cyc
pin and will not indicate when an internal reset has occurred.
3.6.3 Com p ute r Op e ra ting Prop e rly (COP) Re se t
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to timeout, an internal reset is generated
to reset the MCU. Because the internal reset signal is used, the MCU
General Release Specification
MC68HC05E1 — Revision 2.0
CPU Core
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