Freescale Semiconductor, Inc.
CPU Core
Addressing Modes
3.5.7 Ind e xe d , 16-Bit Offse t
In the indexed, 16-bit offset addressing mode, the effective address is
the sum of the contents of the unsigned 8-bit index register and the two
unsigned bytes following the opcode. This address mode can be used in
a manner similar to indexed, 8-bit offset except that this three-byte
instruction allows tables to be anywhere in memory. As with direct and
extended addressing, the Motorola assembler determines the shortest
form of indexed addressing.
3.5.8 Bit Se t/ Cle a r
In the bit set/clear addressing mode, the bit to be set or cleared is part
of the opcode, and the byte following the opcode specifies the direct
address of the byte in which the specified bit is to be set or cleared. Any
read/write bit in the first 256 locations of memory, including I/O, can be
selectively set or cleared with a single two-byte instruction.
3.5.9 Bit Te st a nd Bra nc h
The bit test and branch addressing mode is a combination of direct
addressing and relative addressing. The bit that is to be tested and its
condition (set or clear), is included in the opcode. The address of the
byte to be tested is in the single byte immediately following the opcode
byte. The signed relative 8-bit offset in the third byte is added to the PC
if the specified bit is set or cleared in the specified memory location. This
single three-byte instruction allows the program to branch based on the
condition of any readable bit in the first 256 locations of memory. The
span of branching is from -128 to +127 from the address of the next
opcode. The state of the tested bit is also transferred to the carry bit of
the condition code register.
MC68HC05E1 — Revision 2.0
General Release Specification
CPU Core
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