Freescale Semiconductor, Inc.
CPU Core
3.8 Low-Powe r Mod e s
3.8.1 STOP
The STOP instruction places the MCU in its lowest power consumption
mode. In STOP mode, the internal oscillator is turned off, halting all
internal processing, including timer (and COP Watchdog timer)
operation.
The I bit in the CCR is cleared to enable external interrupts. All other
registers, including the remaining bits in the TCSR, and memory remain
unaltered. All input/output lines remain unchanged. The processor can
be brought out of the STOP mode only by an external interrupt or
RESET.
The STOP instruction can be disabled by a mask option. When disabled,
the STOP instruction is executed as a NOP.
See 6.6 Operation During STOP Mode.
3.8.2 WAIT
The WAIT instruction places the MCU in a low-power consumption
mode, but the WAIT mode consumes more power than the STOP mode.
All CPU action is suspended, but the timer remains active. An interrupt
from the timer can cause the MCU to exit the WAIT mode.
During the WAIT mode, the I bit in the CCR is cleared to enable
interrupts. All other registers, memory, and input/output lines remain in
their previous state. The timer may be enabled to allow a periodic exit
from the WAIT mode.
See 6.7 Operation During WAIT Mode.
General Release Specification
MC68HC05E1 — Revision 2.0
CPU Core
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