Design Considerations
Table 35. I 2C Timing (continued)
Characteristic
Symbol
Standard Mode
Minimum Maximum
300
Fast Mode
Unit
Minimum Maximum
5
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
20 +0.1Cb
0.6
300
—
ns
µs
µs
tSU; STO
tBUF
4
—
—
Bus free time between STOP and
START condition
4.7
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU; DAT
1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
6. Cb = total capacitance of the one bus line in pF.
=
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tHD; STA
tSU; STO
S
SR
P
S
tHD; DAT
tHIGH
Figure 22. Timing Definition for Fast and Standard Mode Devices on the I2C Bus
9 Design Considerations
9.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RΘJA x PD)
Where,
TA = Ambient temperature for the package (°C)
RΘJA = Junction-to-ambient thermal resistance (°C/W)
PD = Power dissipation in the package (W)
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
58
Freescale Semiconductor, Inc.
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