PWMs and timers
RXD
SCI receive
data pin
RXD
PW
(Input)
Figure 19. RXD Pulse Width
TXD
SCI transmit
data pin
TXD
PW
(output)
Figure 20. TXD Pulse Width
8.7.3 Freescale’s Scalable Controller Area Network (FlexCAN)
Table 34. FlexCAN Timing Parameters
Characteristic
Baud Rate
Symbol
BRCAN
Min
—
—
5
Max
1
Unit
Mbps
µs
CAN Wakeup dominant pulse filtered
CAN Wakeup dominant pulse pass
TWAKEUP
TWAKEUP
2
—
µs
CAN_RX
CAN receive
data pin
T
WAKEUP
(Input)
Figure 21. Bus Wake-up Detection
8.7.4 Inter-Integrated Circuit Interface (I2C) Timing
Table 35. I 2C Timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
Data set-up time
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
6
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
Table continues on the next page...
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
57
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