PWMs and timers
SS
(Input)
SS is held High on master
t
C
t
F
t
R
t
CL
SCLK (CPOL = 0)
(Output)
t
CH
t
F
t
CL
SCLK (CPOL = 1)
(Output)
t
CH
t
DS
t
R
t
DH
MISO
(Input)
MSB in
t
Bits 14–1
LSB in
t
(ref)
DI
t
DV
t (ref)
DV
DI
MOSI
(Output)
Master MSB out
Bits 14– 1
Master LSB out
t
t
R
F
Figure 16. SPI Master Timing (CPHA = 1)
SS
(Input)
t
C
t
F
t
ELG
t
CL
t
R
SCLK (CPOL = 0)
(Input)
t
CH
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
CH
t
F
t
t
A
R
t
D
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DS
DV
t
t
DI
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 17. SPI Slave Timing (CPHA = 0)
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
55
Preliminary
General Business Information
FREESCALE [ Freescale ]
