PWMs and timers
SS
(Input)
t
F
t
C
t
R
t
CL
SCLK (CPOL = 0)
(Input)
t
CH
t
ELG
t
ELD
t
CL
SCLK (CPOL = 1)
(Input)
t
t
DV
CH
t
R
t
t
D
t
A
F
MISO
(Output)
Slave MSB out
Bits 14–1
Slave LSB out
t
t
DV
DS
t
DI
t
DH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 18. SPI Slave Timing (CPHA = 1)
8.7.2 Queued Serial Communication Interface (SCI) Timing
Parameters listed are guaranteed by design.
Table 33. SCI Timing
Characteristic
Baud rate1
Symbol
BR
Min
—
Max
Unit
Mbps
ns
See Figure
—
(fMAX/16)
1.04/BR
1.04/BR
RXD pulse width
TXD pulse width
RXDPW
TXDPW
0.965/BR
0.965/BR
Figure 19
Figure 20
ns
LIN Slave Mode
Deviation of slave node clock from nominal FTOL_UNSYNCH
clock rate before synchronization
-14
14
2
%
%
—
—
Deviation of slave node clock relative to
the master node clock after
synchronization
FTOL_SYNCH
-2
Minimum break character length
TBREAK
13
11
—
—
Master
node bit
periods
—
—
Slave node
bit periods
1. fMAX is the frequency of operation of the SCI clock in MHz, which can be selected system clock (max. 160 MHz depending
on part number) or 2x system clock (max. 200 MHz) for the devices.
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
56
Freescale Semiconductor, Inc.
Preliminary
General Business Information
FREESCALE [ Freescale ]
