PWMs and timers
Table 32. SPI Timing (continued)
Characteristic
Enable lead time
Master
Symbol
Min
Max
Unit
See Figure
tELD
Figure 18
—
—
—
ns
ns
Slave
17.5
Enable lag time
Master
tELG
Figure 18
—
—
—
ns
ns
Slave
17.5
Clock (SCK) high time
Master
tCH
Figure 15
Figure 16
Figure 17
Figure 18
Figure 18
20
20
—
—
ns
ns
Slave
Clock (SCK) low time
tCL
Master
20
20
—
—
ns
ns
Slave
Data set-up time required for inputs
tDS
Figure 15
Figure 16
Figure 17
Figure 18
Figure 15
Figure 16
Figure 17
Figure 18
Figure 18
Master
Slave
20
1
—
—
ns
ns
Data hold time required for inputs
tDH
Master
Slave
1
3
—
—
ns
ns
Access time (time to data active
from high-impedance state)
tA
5
5
—
—
ns
ns
Slave
Disable time (hold time to high-
impedance state)
tD
Figure 18
Slave
Data valid for outputs
Master
tDV
Figure 15
Figure 16
Figure 17
Figure 18
Figure 15
Figure 16
Figure 17
Figure 18
—
—
6.25
18.7
ns
ns
Slave (after enable edge)
Data invalid
Master
tDI
0
0
—
—
ns
ns
Slave
Table continues on the next page...
MC56F8455x Advance Information Data Sheet, Rev. 2, 06/2012.
Freescale Semiconductor, Inc.
53
Preliminary
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