PPH PPH PPH PPH
Phase A
(Input)
PHL
PIN
PHL
Phase B
(Input)
PHL
PIN
PHL
Figure 10-16 Quadrature Decoder Timing
10.13 Serial Communication Interface (SCI) Timing
1
Table 10-21 SCI Timing
Characteristic
Baud Rate2
Symbol
BR
Min
Max
Unit
Mbps
ns
See Figure
(fMAX/16)
1.04/BR
1.04/BR
—
—
RXD3 Pulse Width
TXD4 Pulse Width
RXDPW
TXDPW
0.965/BR
0.965/BR
10-17
10-18
ns
1. Parameters listed are guaranteed by design.
2. f is the frequency of operation of the system clock, ZCLK, in MHz, which is 60MHz for the 56F8367 device , and
MAX
40MHz for the 56F8167 device.
3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
RXD
SCI receive
data pin
RXDPW
(Input)
Figure 10-17 RXD Pulse Width
TXD
SCI receive
data pin
TXDPW
(Input)
Figure 10-18 TXD Pulse Width
56F8367 Technical Data, Rev. 9
158
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
