Peripheral Memory Mapped Registers
Table 4-29 GPIOA Registers Address Map (Continued)
(GPIOA_BASE = $00 F2E0)
Address Offset
$9
$A
Register Description
Push-Pull Mode Register
Raw Data Input Register
Reset Value
0 x 3FFF
—
Register Acronym
GPIOA_PPMODE
GPIOA_RAWDATA
Table 4-30 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOB_PUR
GPIOB_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
0 x 00FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 00FF
—
Data Register
GPIOB_DDR
GPIOB_PER
GPIOB_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
GPIOB_IENR
GPIOB_IPOLR
GPIOB_IPR
GPIOB_IESR
GPIOB_PPMODE
GPIOB_RAWDATA
Table 4-31 GPIOC Registers Address Map
(GPIOC_BASE = $00 F310)
Register Acronym
Address Offset
Register Description
Pull-up Enable Register
Reset Value
GPIOC_PUR
GPIOC_DR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
0 x 07FF
0 x 0000
0 x 0000
0 x 07FF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 07FF
Data Register
GPIOC_DDR
GPIOC_PER
GPIOC_IAR
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
GPIOC_IENR
GPIOC_IPOLR
GPIOC_IPR
GPIOC_IESR
GPIOC_PPMODE
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary
65
FREESCALE [ Freescale ]
