Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Active
Peripheral Clocks
Description
Device is fully functional
Run
Wait
Active
Active
Core and memory
clocks disabled
Peripherals are active and can produce interrupts if
they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in The only possible recoveries from Stop mode are:
the SIM, but most are gated prior to
reaching memory, core and peripherals.
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as
the main processor frequency in this architecture. The maximum frequency of operation is
SYS_CLK = 60MHz.
6.8 Stop and Wait Mode Disable Function
Permanent
Disable
D
Q
D-FLOP
C
56800E
Reprogrammable
Disable
STOP_DIS
D
Q
D-FLOP
Clock
Select
C
R
Note: Wait disable circuit is similar
Reset
Figure 6-16 Internal Stop Disable Circuit
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For lowest
power consumption in Stop mode, the PLL can be shut down. This must be done explicitly before entering
Stop mode, since there is no automatic mechanism for this. When the PLL is shut down, the 56800E
system clock must be set equal to the oscillator output.
56F8345 Technical Data, Rev. 17
120
Freescale Semiconductor
Preliminary
FREESCALE [ Freescale ]
