Reset Values
Add.
Offset
Register Acronym
GPIOD_PUPEN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PU[15:0]
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
R
W
D[15:0]
GPIOD_DATA
GPIOD_DDIR
RS
0
0
R
W
DD[15:0]
RS
0
0
R
W
PE[15:0]
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
RS
1
1
R
W
IA[15:0]
RS
0
0
R
W
IEN[15:0]
RS
0
0
R
W
IEPOL[15:0]
GPIOD_IEPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
RS
0
0
R
W
IPR[15:0]
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
0
0
0
0
1
0
0
1
X
0
R
W
IES[15:0]
RS
0
0
R
W
OEN[15:0]
RS
1
1
R
W
RAW DATA[15:0]
RS
X
X
X
X
R
W
DRIVE[15:0]
RS
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-4 GPIOD Register Map Summary
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
121
FREESCALE [ Freescale ]
