Register Descriptions
Base + $19
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
IPS1_DSYNC1
0
IPS1_DSYNC0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)
6.3.22.1 Reserved—Bits 15–7
This bit field is reserved. Each bit must be set to 0.
6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1
(IPS1_DSYNC1)—Bits 6–4
This field selects the alternate input source signal to feed DAC1 SYNC input.
•
•
•
•
•
•
•
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
6.3.22.3 Reserved—Bit 3
This bit field is reserved. Each bit must be set to 0.
6.3.22.4 Select Input Peripheral Source for SYNC Input to DAC 0
(IPS1_DSYNC0)—Bits 2–0
This field selects the alternate input source signal to feed DAC0 SYNC input.
•
•
•
•
•
•
•
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A
(SIM_IPS2)
See Section 6.3.21 for general information about Internal Peripheral Source Select registers.
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
105
FREESCALE [ Freescale ]
