Part 1 Overview
1.1 56F8013/56F8011 Features
1.1.1
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Digital Signal Controller Core
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16
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16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2
Differences Between Devices
outlines the key differences between the 56F8013 and 56F8011 devices.
Table 1-1 Device Differences
Feature
Program Flash
Unified Data/Program RAM
56F8013
16KB
4KB
56F8011
12KB
2KB
1.1.3
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Memory
Dual Harvard architecture permits as many as three simultaneous accesses to program and data
memory
Flash security and protection that prevent unauthorized users from gaining access to the internal
Flash
On-chip memory:
— 16KB of Program Flash (56F8013 device)
12KB of Program Flash (56F8011 device)
— 4KB of Unified Data/Program RAM (56F8013 device)
2KB of Unified Data/Program RAM (56F8011 device)
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EEPROM emulation capability using Flash
56F8013/56F8011 Data Sheet, Rev. 10
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Freescale Semiconductor
Preliminary
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
