56F8013/56F8011 General Description
Note:
Features in italics describe the 56F8011 device.
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8013 device offers 16KB Program Flash
56F8011 device offers 12KB Program Flash
• 56F8013 device offers 4KB Unified Data/Program
RAM
56F8011 device offers 2KB Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) Port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET
V
CAP
4
JTAG/EOnCE
Port or
GPIOD
V
DD
V
SS
2
V
DDA
V
SSA
7
PWM Outputs
PWM
or Timer Port
or GPIOA
Program Controller
and Hardware
Looping Unit
Digital Reg
Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
3
AD0
3
ADC
or
GPIOC
PAB
PDB
CDBR
CDBW
Memory
Program Memory
8K x 16 Flash
6K x 16 Flash
Unified Data /
Program RAM
4KB
2KB
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD1
System Bus
Control
IPBus Bridge (IPBB)
2
Timer or
GPIOB
SPI or I
2
C
or Timer
or GPIOB
4
SCI
or I
2
C
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
*Includes On-Chip
Relaxation Oscillator
56F8013/56F8011 Block Diagram
56F8013/56F8011 Data Sheet, Rev. 10
4
Freescale Semiconductor
Preliminary
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
