DSP56800E Core
Program Control Unit
ALU1
ALU2
Address
PC
LA
LA2
Generation
Unit
Instruction
Decoder
R0
R1
(AGU)
HWS0
HWS1
FIRA
R2
R3
Interrupt
Unit
Program
Memory
M01
N3
OMR
R4
R5
N
SR
LC
LC2
Looping
Unit
SP
FISR
XAB1
XAB2
PAB
Data /
Program
RAM
PDB
CDBW
CDBR
XDB2
A2
B2
C2
D2
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Bit-
Manipulation
Unit
IPBUS
Interface
Y
Data
Enhanced
OnCE™
Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU
Multi-Bit Shifter
Figure 1-1 56800E Core Block Diagram
56F8013/56F8011 Data Sheet, Rev. 10
10
Freescale Semiconductor
Preliminary