FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
DEVICE REGISTER ADDRESSING
Table 11. Over-current Low Detection Levels
The following section describes the possible register
addresses and their impact on device operation.
SOCL2
(D2)
SOCL1
(D1)
SOCL0
(D0)
Over-current Low Detection
(Amperes)
Address x000—Status Register (STATR)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
22.5
20
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2:D0, determine the content of the first eight bits of SO data.
When register content is specific to one of the two outputs, bit
D7 is used to select the desired output (SOA3). In addition to
the device status, this feature provides the ability to read the
content of the OCR, SOCHLR, CDTOLR, DICR, OSDR,
WDR, NAR, and UOVR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data).)
17.5
15
12.5
10
7.5
Table 12. Over-current High Detection Levels
Address x001—Output Control Register (OCR)
Over-current High Detection
SOCH (D3)
The OCR register allows the MCU to control the outputs
through the SPI. Incoming message bit D0 reflects the
desired states of the high side output HS0 (IN0_SPI): a
Logic [1] enables the output switch and a Logic [0] turns it
OFF. A Logic [1] on message bit D1 enables the Current
Sense (CSNS) pin. Similarly, incoming message bit D2
reflects the desired states of the high side output HS1
(IN1_SPI): Logic [1] enables the output switch and a Logic [0]
turns it OFF. A Logic [1] on message bit D3 enables the
CSNS pin. In the event that the current sense is enabled for
both outputs, the current will be summed. Bit D7 is used to
feed the watchdog if enabled.
(Amperes)
0
1
100
75
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state
of the D7 bit. A write to this register when bit 7 is Logic [0] will
configure the timeout for the HS0. Similarly, if D7 is Logic [1]
when this register is written, then HS1 is configured. Bits
D1:D0 allow the MCU to select one of four fault blanking
times defined in Table 13. Note that these time-outs apply
only to the over-current low detection levels. If the selected
over-current high level is reached, the device will latch off
within 20 μs.
Address x010— Select Over-current High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output over-current low and high detection levels,
respectively. Each output is independently selected for
configuration based on the state of the D7 bit; a write to this
register when D7 is Logic [0] will configure the current
detection levels for the HS0. Similarly, if D7 is Logic [1] when
this register is written, HS1 is configured. Each output can be
configured to different levels. In addition to protecting the
device, this slow blow fuse emulation feature can be used to
optimize the load requirements matching system
characteristics. Bits D2:D0 set the over-current low detection
level to one of eight possible levels, as shown in Table 11.
Bit D3 sets the over-current high detection level to one of two
levels, which is described inTable 12.
Table 13. Over-current Low Detection Blanking Time
OCLT[1:0]
Timing
00
01
10
11
155 ms
10 ms
1.2 ms
150 μs
A Logic [1] on bit D2 disables the over-current low
(CD_dis) detection timeout feature. A Logic [1] on bit D3
disables the open load (OL) detection feature.
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
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