FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
The FS pin will automatically return to Logic [1] when the
fault condition is removed, except for over-current and in
some cases under-voltage.
FAULT MODE
The 33984 indicates the following faults as they occur by
driving the FS pin to Logic [0]:
Fault information is retained in the fault register and is
available (and reset) via the SO pin during the first valid SPI
communication (refer to Table 17).
• Over-temperature fault
• Open load fault
• Over-current fault (high and low)
• Over-voltage and under-voltage fault
PROTECTION AND DIAGNOSIS FEATURES
report any under-voltage fault condition and the output state
will not be changed as long as battery voltage does not drop
any lower than 2.5 V.
OVER-TEMPERATURE FAULT (NON-LATCHING)
The 33984 incorporates over-temperature detection and
shutdown circuitry in each output structure. Over-
temperature detection is enabled when an output is in the ON
state.
OPEN LOAD FAULT (NON-LATCHING)
The 33984 incorporates open load detection circuitry on
each output. Output open load fault (OLF) is detected and
reported as a fault condition when that output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
For the output, an over-temperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or
until the offending load is removed.
When experiencing this fault, the OTF fault bit will be set
in the status register and cleared after either a valid SPI read
or a power reset of the device.
The open load protection can be disabled trough SPI (bit
OL_dis). It is recommended to disable the open load
detection circuitry (OL_dis bit sets to logic [1]) in case
of permanent open load fault condition.
OVER-VOLTAGE FAULT (NON-LATCHING)
The 33984 shuts down the output during an over-voltage
fault (OVF) condition on the VPWR pin. The output remains
in the OFF state until the over-voltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the bit
OD1 and cleared after either a valid SPI read or a power reset
of the device.
OVER-CURRENT FAULT (LATCHING)
The device has eight programmable over-current low
detection levels (IOCL) and two programmable over-current
high detection levels (IOCH) for maximum device protection.
The two selectable, simultaneously active over-current
detection levels, defined by IOCH and IOCL, are illustrated in
Figure 6. The eight different over-current low detect levels
(IOCL0:IOCL7) are likewise illustrated in Figure 6.
The over-voltage protection and diagnostic can be
disabled trough the SPI (bit OV_dis).
UNDER-VOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
If the load current level ever reaches the selected over-
current low detect level and the over-current condition
exceeds the programmed over-current time period (tOCx), the
device will latch the effected output OFF.
The output(s) will latch off at some battery voltage below
6.0 V. As long as the VDD level stays within the normal
specified range, the internal logic states within the device will
be sustained.
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCL driver.
In the case where battery voltage drops below the under-
voltage threshold (VPWRUV) output will turn off, FS will go to
Logic [0], and the fault register UVF bit will be set to 1.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
Two cases need to be considered when the battery level
recovers :
• If output(s) command is (are) low, FS will go to Logic [1]
but the UVF bit will remain set to 1 until the next read
operation.
• If the output command is ON, then FS will remain at
Logic [0]. The output must be turned OFF and ON again
to re-enable the state of output and release FS . The
UVF bit will remain set to 1 until the next read operation.
REVERSE BATTERY
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gates are
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required.
The under-voltage protection can be disabled through the
SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FREESCALE [ Freescale ]
