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33984B_09 参数 Datasheet PDF下载

33984B_09图片预览
型号: 33984B_09
PDF下载: 下载PDF文件 查看货源
内容描述: 双智能大电流自我保护的硅的高边开关( 4.0毫欧) [Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mΩ)]
分类和应用: 开关
文件页数/大小: 38 页 / 853 K
品牌: FREESCALE [ Freescale ]
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FUNCTIONAL DEVICE OPERATION  
LOGIC COMMANDS AND REGISTERS  
to the MCU during the first SPI communication following  
this condition should be ignored.  
SERIAL OUTPUT COMMUNICATION  
(DEVICE STATUS RETURN DATA)  
When the CS pin is pulled low, the output status register is  
loaded. Meanwhile, the data is clocked out MSB- (OD7-) first  
as the new message data is clocked into the SI pin. The first  
eight bits of data clocking out of the SO, and following a CS  
transition, are dependant upon the previously written SPI  
word.  
SERIAL OUTPUT BIT ASSIGNMENT  
The 8 bits of serial output data depend on the previous  
serial input message, as explained in the following  
paragraphs. Table 16 summarizes the SO register content.  
Bit OD7 reflects the state of the watchdog bit (D7)  
addressed during the prior communication. The value of the  
previous D7 will determine which output the status  
information applies to for the Fault (FLTR), SOCHLR,  
CDTOLR, and DICR registers. SO data will represent  
information ranging from fault status to register contents,  
user selected by writing to the STATR bits D2:D0. Note that  
the SO data will continue to reflect the information for each  
output (depending on the previous D7 state) that was  
selected during the most recent STATR write until changed  
with an updated STATR write.  
Any bits clocked out of the SO pin after the first eight will  
be representative of the initial message bits clocked into the  
SI pin since the CS pin first transitioned to a Logic [0]. This  
feature is useful for daisy chaining devices as well as  
message verification.  
A valid message length is determined following a CS  
transition of Logic [0] to Logic [1]. If there is a valid message  
length, the data is latched into the appropriate registers. A  
valid message length is a multiple of eight bits. At this time,  
the SO pin is tri-stated and the fault status register is now  
able to accept new fault status information.  
Previous Address SOA[2:0]=000  
The output status register correctly reflects the status of  
the STATR-selected register data at the time that the CS is  
pulled to a Logic [0] during SPI communication and/or for the  
period of time since the last valid SPI communication, with  
the following exceptions:  
If the previous three MSBs are 000, bits OD6:OD0 will  
reflect the current state of the Fault register (FLTR)  
corresponding to the output previously selected with the bit  
OD7 (Table 17).  
• The previous SPI communication was determined to be  
invalid. In this case, the status will be reported as  
though the invalid SPI communication never occurred.  
• Battery transients below 6.0 V resulting in an under-  
voltage shutdown of the outputs may result in incorrect  
data loaded into the status register. The SO data  
transmitted to the MCU during the first SPI  
Previous Address SOA[2:0]=001  
Data in bits OD1:OD0 contain CSNS0 EN and IN0_SPI  
programmed bits, respectively. Data in bits OD3:OD2 contain  
CSNS0 EN and IN0_SPI programmed bits, respectively.  
Previous Address SOA[2:0]=010  
communication following an under-voltage VPWR  
condition should be ignored.  
• The RST pin transition from a Logic [0] to Logic [1] while  
the WAKE pin is at Logic [0] may result in incorrect data  
loaded into the status register. The SO data transmitted  
The data in bit OD3 contain the programmed over-current  
high detection level (refer to Table 12), and the data in bits  
OD2:OD0 contain the programmed over-current low  
detection levels (refer to Table 13).  
Table 16. Serial Output Bit Map Description  
Previous STATR  
D7, D2, D1, D0  
Serial Output Returned Data  
SOA3 SOA2 SOA1 SOA0  
OD7  
OD6  
OD5  
OD4  
OD3  
OD2  
OD1  
OD0  
s
x
s
s
s
0
1
0
1
x
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
s
x
s
s
s
0
1
0
1
OTFs  
OCHFs  
OCLFs  
OLFs  
UVF  
OVF  
CSNS0 EN  
SOCL1s  
OCLT1s  
IN DIS s  
OSD1  
FAULTs  
IN0_SPI  
SOCL0s  
OCLT0s  
A/Os  
0
0
0
1
1
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
1
1
0
0
CSNS1 EN  
SOCHs  
IN1_SPI  
SOCL2s  
CD_DIS s  
OL_DIS s  
FAST SR s CSNS high s  
FSM_HS0  
FSM_HS1  
IN1 Pin  
OSD2  
WDTO  
IN0 Pin  
OSD0  
WD1  
WD0  
FSI Pin  
UV_dis  
WAKE Pin  
OV_dis  
See Table 1  
s = Selection of output: Logic [0] = HS0, Logic [1] = HS1.  
x = Don’t care.  
33984  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
27