FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
to D0. The internal registers of the 33984 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 9. Register addressing and configuration are described
in Table 10. The SI input has an active internal pull-down,
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
IDWN
.
The SI/SO pins of the 33984 follow a first-in first-out (D7/
D0) protocol with both input and output words transferring the
most significant bit (MSB) first. All inputs are compatible with
5.0 V CMOS logic levels.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CS pin is put into a Logic [0] state. The SO data is capable
of reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes states on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and Input Status descriptions are provided in
Table 6.
The SPI lines perform the following functions:
SERIAL CLOCK (SCLK)
Serial clocks (SCLK) the internal shift registers of the
33984 device. The serial input (SI) pin accepts data into the
input shift register on the falling edge of the SCLK signal
while the serial output (SO) pin shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic low state whenever
CS makes any transition. For this reason, it is recommended
that the SCLK pin be in a Logic [0] state whenever the device
is not accessed (CS Logic [1] state). SCLK has an active
internal pull-down, IDWN. When CS is Logic [1], signals at the
SCLK and SI pins are ignored and SO is tri-stated (high-
impedance). See Figure 9 and Figure 10.
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a Logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33984 device
latches in data from the Input shift registers to the addressed
registers on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS
is Logic [0]. CS should transition from a Logic [1] to a Logic [0]
state only when SCLK is a Logic [0]. CS has an active internal
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. SI
instruction is read on the falling edge of SCLK. An 8-bit
stream of serial data is required on the SI pin, starting with D7
pull-up, IUP
.
CSB
CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
NOTES: 1. RRSSTTB is in a logic 1 state during the above operation.
Notes 1. RST is a Logic [1] state during the above operation.
2. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
of the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 9. Single 8-Bit Word SPI Communication
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FREESCALE [ Freescale ]
