FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33984 is a dual self-protected 4.0 mΩ silicon switch
used to replace electromechanical relays, fuses, and discrete
devices in power management applications. The 33984 is
designed for harsh environments, and it includes self-
recovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented
via the Serial Peripheral Interface (SPI). A dedicated parallel
input is available for alternate and Pulse Width Modulation
(PWM) control of each output. SPI-programmable fault trip
thresholds allow the device to be adjusted for optimal
performance in the application.
The 33984 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
circuit and fail-safe operation are disabled. This pin
incorporates an active internal pull-up current source.
OUTPUT CURRENT MONITORING (CSNS)
This pin is used to output a current proportional to the
designated HS0-1 output. That current is fed into a ground-
referenced resistor and its voltage is monitored by an MCU's
A/D. The channel to be monitored is selected via the SPI.
This pin can be tri-stated through the SPI.
CHIP SELECT (CS)
This input pin is connected to a chip select output of a
master microcontroller (MCU). The MCU determines which
device is addressed (selected) to receive data by pulling the
CS pin of the selected device Logic LOW, enabling SPI
communication with the device. Other unselected devices on
the serial link having their CS pins pulled-up Logic HIGH
disregard the SPI communication data sent. This pin
incorporates an active internal pull-up current source.
WAKE (WAKE)
This pin is used to input a Logic [1] signal so as to enable
the watchdog timer function. An internal clamp protects this
pin from high damaging voltages when the output is current
limited with an external resistor. This input has a passive
internal pull-down.
SERIAL CLOCK (SCLK)
This input pin is connected to the MCU providing the
required bit shift clock for SPI communication. It transitions
one time per bit transferred at an operating frequency, fSPI
defined by the communication interface. The 50 percent duty
cycle CMOS-level serial clock signal is idle between
command transfers. The signal is used to shift data into and
out of the device. This input has an active internal pull-down
current source.
RESET (RST)
This input pin is used to initialize the device configuration
and fault registers, as well as place the device in a low-
current Sleep mode. The pin also starts the watchdog timer
when transitioning from Logic LOW to Logic HIGH. This pin
should not be allowed to be Logic HIGH until VDD is in
regulation. This pin has a passive internal pull-down.
,
DIRECT IN 0 & 1 (INx)
SERIAL INPUT (SI)
This input pin is used to directly control the output HS0 and
1. This input has an active internal pull-down current source
and requires CMOS logic levels. This input may be
configured via the SPI.
This is a command data input pin connected to the SPI
Serial Data Output of the MCU or to the SO pin of the
previous device of a daisy chain of devices. The input
requires CMOS logic-level signals and incorporates an active
internal pull-down current source. Device control is facilitated
by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the
falling edge of SCLK. The logic state of SI present upon the
rising edge of SCLK loads that bit command into the internal
command shift register.
FAULT STATUS (FS)
This is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. When a
device fault condition is detected, this pin is active LOW.
Specific device diagnostic faults are reported via the SPI SO
pin.
DIGITAL DRAIN VOLTAGE (VDD)
FAIL-SAFE INPUT (FSI)
This is an external voltage input pin used to supply power
to the SPI circuit. In the event VDD is lost, an internal supply
provides power to a portion of the logic, ensuring limited
functionality of the device. All device configuration registers
are reset.
The value of the resistance connected between this pin
and ground determines the state of the outputs after a
watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF, ON, or the output HS0 only
is ON. When the FSI pin is connected to GND, the watchdog
33984
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FREESCALE [ Freescale ]
