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33910_10 参数 Datasheet PDF下载

33910_10图片预览
型号: 33910_10
PDF下载: 下载PDF文件 查看货源
内容描述: LIN系统基础芯片,高 [LIN System Basis Chip with High]
分类和应用:
文件页数/大小: 90 页 / 1134 K
品牌: FREESCALE [ Freescale ]
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MC33910G5AC/MC3433910G5AC  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 5. Dynamic Electrical Characteristics  
Characteristics noted under conditions 5.5 V VSUP 18 V, -40°C TA 125°C for the 33910 and -40°C TA 85°C for the  
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal  
conditions, unless otherwise noted.  
Characteristic  
SPI INTERFACE TIMING (SEE Figure 13)  
Symbol  
Min  
Typ  
Max  
Unit  
SPI Operating Frequency  
f
t
4.0  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
MHz  
ns  
SPIOP  
SCLK Clock Period  
250  
110  
110  
100  
100  
40  
CLK  
PS  
SCLK Clock High Time(42)  
t
ns  
SCLKH  
W
SCLK Clock Low Time(42)  
t
ns  
SCLKL  
W
Falling Edge of CS to Rising Edge of SCLK(42)  
Falling Edge of SCLK to CS Rising Edge(42)  
MOSI to Falling Edge of SCLK(42)  
Falling Edge of SCLK to MOSI(42)  
MISO Rise Time(42)  
t
ns  
LEAD  
tLAG  
ns  
t
ns  
SISU  
t
40  
ns  
SIH  
tRSO  
ns  
C = 220 pF  
L
40  
40  
MISO Fall Time(42)  
t
ns  
ns  
FSO  
C = 220 pF  
L
Time from Falling or Rising Edges of CS to:(42)  
- MISO Low-impedance  
t
0.0  
0.0  
50  
50  
SOEN  
- MISO High-impedance  
t
SODIS  
Time from Rising Edge of SCLK to MISO Data Valid(42)  
t
ns  
VALID  
0.2 x VDD MISO 0.8 x VDD, CL = 100 pF  
0.0  
75  
RST OUTPUT PIN  
Reset Low-level Duration After VDD High (see Figure 12)  
Reset Deglitch Filter Time  
t
0.65  
350  
1.0  
1.35  
900  
ms  
ns  
RST  
t
480  
RSTDF  
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)  
Watchdog Time Period(43)  
t
ms  
PWD  
External Resistor REXT = 20 kΩ (1%)  
External Resistor REXT = 200 kΩ (1%)  
Without External Resistor REXT (WDCONF Pin Open)  
8.5  
79  
10  
94  
11.5  
108  
205  
110  
150  
Notes  
42. This parameter is guaranteed by process monitoring but not production tested.  
43. Watchdog timing period calculation formula: tPWD [ms] = [0.466 * (REXT - 20)] + 10 with (REXT in kΩ)  
33910  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
16  
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