ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
33874
THERMAL ADDENDUM (REV 2.0)
Introduction
This thermal addendum is provided as a supplement to the 33874 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
HIGH SIDE SWITCH
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RθJAmn
.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to RθJ21
and RθJ22, respectively.
PNA SUFFIX
98ART10510D
24-PIN PQFN (12 x 12)
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
Note For package dimensions, refer to
the 33874 data sheet.
.
=
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained
by measurement and simulation according to the standards listed below.
Table 18. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
1.0
(1), (2)
R
20
6
16
2.0
40
39
26
73
1.0
0.2
θJAmn
θJBmn
θJAmn
θJCmn
1.0
(2), (3)
(1), (4)
(5)
R
R
R
53
0.2
<0.5
0.0
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
Figure 10. Testboard According to JEDEC
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
FREESCALE [ Freescale ]
